RIE and plasma etching techniques have been widely used for etching products such as semiconductor wafers. Basically such a technique comprises exposing the wafers to the plasma to remove, in selected regions, selected surface materials, such as silicon dioxide, carried on the semiconductor wafer surface. Polymeric materials, such as photoresist, are used as etch masks to prevent unwanted etching. Because the etch process determines if etching is done in a chemical or physical mode, etching of the selected materials can be very closely controlled.
Although the etching tools presently used are greatly improved over those in the past, and the gas flow, pressure, and temperature as well as the gross electric fields, and plasma formation is more closely controlled than was possible in the past, asymmetrical etching may still occur during the process.
RIE or plasma etching occurs because the ions doing the etching are extracted from the plasma by the electric field existing between the wafer, the pedestal and the plasma sheath, i.e., the edges of the plasma cloud. The ions extracted from the plasma follow the electric field lines to impact on and react with the selected exposed regions on the face of the wafer. Ideally these electric field lines should be normal to the surface of the wafer over its entire face. However, in apparatus used in the industry the edges of the wafer and pedestal, and the wafer hold down clips, used in some apparatus, each induce distortion or variations in the direction of the electrical field lines between the plasma sheath, the wafer, the pedestal and the clips. The angling of the wafer pedestals exacerbates electric field and plasma sheath distortion. Thus, the pedestal design can increase the non-normality of the electric fields at and near the edges of the wafer. Such electrical field variation causes the ions, drawn out of the plasma and effecting the etching, to interact with the wafer surface at acute or obtuse angles to the surface of the wafer. Any non-normal angle of incidence of the ions causes asymmetrical etching to occur in the wafer. Such asymmetrical etching is especially acute around the periphery of the wafer because of the high plasma sheath and electrical field line distortion caused by the wafer and pedestal edges.
Many attempts to address problems of non-uniformity have been tried in the past. These attempts include spacing the wafers from the cathode with quartz spacers, curving the surface of the wafer, altering the plasma gas flow, and when large area flat anodes were used, providing tailored wafer pedestals that were varied in direction with respect to the geographical position of the wafer on the cathode. Also the apparatus was itself altered by discarding the large flat plate of the prior art, and substituting therefor a centrally located hexagonal post upon which the wafers were affixed in a substantially vertical direction.
The solutions discussed above did result in improvements to the overall etching uniformity. However, symmetry of etching over the entire surface of the wafer was not realized.
As the demand for increasingly dense semiconductor devices has increased, even the slightest variation in the symmetry of the etched holes in the surface becomes problematic resulting in even more defective devices. Although the addition of the annulus, as taught in the above identified related application, greatly improves the symmetry of the etched holes it has now been found that the presence of the annulus appears to alter the amount, mixture, or distribution of the etching gas or gases in a region immediately adjacent the annulus. This region will herein after be referred to as the "gas depletion region". In this gas depletion region, there is decreased removal of the material being etched, thus causing the slope of the side walls of the etched holes, around the periphery of the wafer, to be considerably steeper than the walls of the etched holes in the center of the wafer.